As a prior art technique to precisely build a stable capacitive element on a semiconductor substrate, a capacitive element comprising double polysilicon layers 4 and 6 as illustrated in FIG. 25 and its cross-sectional view FIG. 26 across the A-A' plane can be mentioned by way of example. As shown in the figures, a dielectric layer 3 is formed on a semiconductor substrate 1, above that a first doped polysilicon layer 4, another dielectric layer 5, and a second polysilicon layer 6 are formed. Note that a well 2 as shown in FIG. 26 is generally used to shield the capacitive element from electrical noises propagated from the semiconductor substrate 1. Further, as shown on FIG. 25, wiring 7A and 7B is connected to the first and second polysilicon layers 4 and 6 via a contact holes 8A and 8B, respectively.
However, since electrodes comprising the capacitive element are semiconductors, depletion layers tend to form on the surface of the electrodes based on the voltage applied, resulting in voltage dependent fluctuations in capacitance of the capacitive element. One of the possible methods to alleviate the above performance fluctuation is to raise the impurity concentration of the polysilicon electrode. Yet, because the polysilicon electrodes of the capacitive element are formed concurrently in a MOS fabrication process, increasing the impurity concentration is not readily allowed just for accommodating needs on the side of the capacitive element alone.
Although there is an alternative method such as one disclosed in the Japanese Patent Application Laid-Open No. 6-69522/1994, wherein the impurity concentration of the region near the surface of electrodes contacting the dielectric layer between the electrode layers is increased to a level higher than the other regions, it will complicate the fabrication steps and therefore increase cost.
As described above, double-layered polysilicon capacitive elements of the prior art have the problem of developing a depletion layer inherent to semiconductor electrodes, and a voltage dependency of the capacitance is unavoidable as long as semiconductor electrodes are used. While there are capacitive elements that employ metal layers for both electrodes, such a type makes it difficult to establish reliability and accuracy for the process of the device.
Accordingly, with an aim at eliminating the above-described problems of the prior art, it is an object of the present invention to provide a semiconductor capacitance device with considerably lower voltage dependency of capacitance, which device is made available without significantly altering the conventional fabrication process, and to provide semiconductor devices using the same.